1. Field of the Invention
The present invention relates to a semiconductor device which is formed by mounting semiconductor packages having integrated circuits on a package substrate.
2. DESCRIPTION OF THE PRIOR ART
FIG. 1A is a plan view showing a small outline package having external lead terminals downwardly bent with respect to a package surface thereof (hereinafter referred to as an A-type package) and FIG. 1B is a side elevational view of the A-type package, while FIG. 1C is a front elevational view of the A-type package and FIG. 1D is a sectional view thereof. As shown in FIG. 1D, a semiconductor chip 2 is placed on a die pad 1. A bonding pad (not shown) provided on the semiconductor chip 2 is electrically connected with external lead terminals 3 by bonding wires 4. The die pad 1, the semiconductor chip 2, parts of the external lead terminals 3 and the bonding wires 4 are packaged by mold resin 5, to form a small outline package 6a whose appearance is as shown in FIGS. 1A to 1C. This package 6a is characterized in that the external lead terminals 3 are downwardly bent at an angle of about 90.degree. with respect to a package surface thereof as shown in FIGS. 1B to 1D, while forward end portions of the external lead terminals 3 are further bent at an angle of about 90.degree. to outwardly extend from the package 6a.
Such forward end portions of the external lead terminals 3 serve as soldering portions 7 to be soldered to a package substrate as hereinafter described. Referring to FIG. 1A, the lower leftmost external lead terminal 3 is referred to as a pin p.sub.1 and the lower rightmost external lead terminal 3 is referred to as a pin p.sub.14, while the upper rightmost external lead terminal 3 is referred to as a pin p.sub.15 and the upper leftmost external lead terminal 3 is referred to as a pin p.sub.28, for convenience of the following description.
FIG. 2 illustrates a semiconductor device having a package substrate 8 which is provided on both surfaces with a pair of A-type packages 6a as shown in FIGS. 1A to 1D. One of the A-type packages 6a is mounted on a first surface of the package substrate 8. The other A-type package 6a is mounted on a second surface of the package substrate 8 in correspondence to the package 6a mounted on the first surface.
FIG. 3 illustrates a semiconductor device having a package substrate 8 which is provided on its one surface with a plurality of A-type packages 6a as shown in FIGS. 1A to 1D. As shown in FIG. 3, such A-type packages 6a are mounted to be substantially parallel to each other.
FIG. 4 is a partially fragmented sectional view for illustrating a method of mounting such a package on the package substrate 8. First, solder 10 is previously applied to a mounting pad 9 of each electrode portion formed on the surface of the package substrate 8, as shown in FIG. 4. Then a package 6a is so mounted on the package substrate 8 as to bring a soldering portion 7 into prescribed positional relation to the mounting pad 9. Thereafter the soldering portion 7 is soldered to the mounting pad 9 to be electrically and mechanically connected to the same by the solder 10, thereby to complete mounting.
Consider such case where a pair of packages 6a are mounted on both surfaces of the package substrate 8 as shown in FIG. 2, so that external lead terminals 3 of the packages 6a having the same pin numbers are connected with each other. In this case, it is impossible to connect the external lead terminals 3 having the same pin numbers by merely connecting the external lead terminals 3 of the pair of packages 6a through holes provided on the package substrate 8. This is because the external lead terminals 3 having the same pin numbers are not rendered opposite to each other in the structure as shown in FIG. 2. For example, the pin p.sub.1 within the external lead terminals 3 of the package 6a mounted on the first surface of the package substrate 8 is rendered opposite to the pin p.sub.14 or p.sub.28 within the external lead terminals 3 of the package 6a provided on the second surface of the package substrate 8.
Further, consider such case where the three or more pairs of external lead terminals 3 having the same pin numbers are connected with each other within those of a pair of packages 6a provided on one surface of the package substrate 8. In this case, it is impossible to connect the external lead terminals 3 of the packages 6a having the same pin umbers with each other by simply drawing around wires 12 on the surface carrying the packages 6a. This is because the wires 12 inevitably intersect with each other in any position to cause a short. When pins p.sub.1, p.sub.14, p.sub.15 and p.sub.28 of the two packages 6a are connected with each other as shown in FIG. 3, for example, the wires 12 inevitably intersect with each other in two positions. Therefore, jumper wires and through holes 13 as shown in FIG. 3 must be provided in such positions, in order to prevent shorting by avoiding such intersection of the wires 12.